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general description the max1887/max1897 step-down slave controllers are intended for low-voltage, high-current, multiphase dc-to- dc applications. the max1887/max1897 slave con- trollers can be combined with any of maxim? quick-pwm step-down controllers to form a multiphase dc-to-dc converter. existing quick-pwm controllers, such as the max1718, function as the master controller, providing accurate output voltage regulation, fast tran- sient response, and fault protection features. synchronized to the master? low-side gate driver, the max1887/max1897 include the quick-pwm constant on- time controller, gate drivers for a synchronous rectifier, active current balancing, and precision current-limit cir- cuitry. the max1887/max1897 provide the same high effi- ciency, ultra-low duty factor capability, and excellent transient response as other quick-pwm controllers. the max1887/max1897 differentially sense the inductor currents of both the master and the slave across cur- rent-sense resistors. these differential inputs and the adjustable current-limit threshold derived from an exter- nal reference allow the slave controller to accurately balance the inductor currents and provide precise cur- rent-limit protection. the max1887/max1897? dual- purpose current-limit input also allows the slave controller to automatically enter a low-power standby mode when the master controller shuts down. the max1887 triggers on the rising edge of the mas- ter? low-side gate driver, which staggers the on-times of both master and slave, providing out-of-phase oper- ation that can reduce the input ripple current and con- sequently the number of input capacitors. the max1897 features a selectable trigger polarity, allowing out-of-phase or simultaneous in-phase operation. applications notebook computers cpu core supply single-stage (batt to v core ) converters two-stage (5v to v core ) converters servers/desktop computers telecom features quick-pwm slave controller precise, active current balance (?.25mv ) accurate, adjustable current-limit threshold optimized for low-output voltages ( 2v) 4v to 28v battery input range fixed 300khz (max1887) or selectable 200khz/300khz/550khz (max1897) switching frequency drive large synchronous-rectifier mosfets 525? (typ) i cc supply current 20? standby supply current <1? shutdown (max1897) supply current small 16-pin qsop (max1887), compact 20-pin 5mm x 5mm qfn (max1897), or 20-pin 5mm x 5mm thin qfn (max1897) max1887/max1897 quick-pwm slave controllers for multiphase, step-down supplies ________________________________________________________________ maxim integrated products 1 20 19 18 17 16 1 2 3 4 5 678910 11 12 13 14 15 thin qfn 5mm x 5mm top view max1897 lx cm+ cm- ton cs- cs+ dh v cc v dd shdn dl pgnd gnd pol comp trig ilim limit v+ bst pin configuration 19-2188; rev 1; 9/02 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. ordering information part temp range pin-package max1887 eee -40 c to +85 c 16 qsop m a x1 8 9 7 e gp* -40 c to +85 c 20 qfn 5mm ? 5mm max1897etp -40 c to +85 c 20 thin qfn 5mm ? 5mm typical operating circuit appears at end of data sheet. pin configurations continued at end of data sheet. quick-pwm is a registered trademark of maxim integrated products, inc. * contact factory for availability.
max1887/max1897 quick-pwm slave controllers for multiphase, step-down supplies 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v+ to gnd ..............................................................-0.3v to +30v v cc , v dd to gnd (note 3) .......................................-0.3v to +6v pgnd to gnd.....................................................................0.3v trig, limit to gnd .................................................-0.3v to +6v shdn to gnd (max1897)........................................-0.3v to +6v ilim, cm+, cm-, cs+, cs-, comp to gnd....................................................-0.3v to (v cc + 0.3v) ton, pol to gnd (max1897) ...................-0.3v to (v cc + 0.3v) dl to pgnd................................................-0.3v to (v dd + 0.3v) bst to gnd ............................................................-0.3v to +36v dh to lx ....................................................-0.3v to (v bst + 0.3v) lx to bst..................................................................-6v to +0.3v continuous power dissipation (t a = +70 c) 16-pin qsop (derate 8.3mw/ c above +70 c)...........667mw 20-pin 5mm x 5mm qfn (derate 20.0mw/ c above +70 c)..............................................................1.60w operating temperature range ...........................-40 c to +85 c junction temperature ......................................................+150 c storage temperature range .............................-65 c to +150 c lead temperature (soldering, 10s) .................................+300 c electrical characteristics (circuit of figure 1, v+ = 15v, v cc = v dd = 5v, v out = v comp = 1.2v, v cm+ = v cm- = v cs+ = v cs- = 1.2v, shdn = v cc (max1897), t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25 c.) parameter symbol conditions min typ max units pwm controller battery voltage, v+ 4.0 28.0 input voltage range v cc , v dd 4.5 5.5 v m ax 1887 ( 300kh z) , v + = 12v , v c om p = 1.2v 320 355 390 ton = gnd 171 190 209 ton = open 320 355 390 on-time (note 1) t on max1897, v+ = 12v, v comp = 1.2v ton = v cc 464 515 566 ns trigger delay (note 2) t trig 75 ns supply currents quiescent supply current (v+) i+ measured at v+; v ilim > 0.35v 25 40 a max1887 525 800 quiescent supply current (v dd ) (note 3) i dd measured at v dd ; v ilim > 0.35v max1897 <1 5 a quiescent supply current (v cc ) (max1897, note 3) i cc measured at v cc ; v ilim > 0.35v 525 800 a standby supply current (v+) measured at v+; ilim = gnd <1 5 a max1887 20 40 standby supply current (v dd ) (note 3) measured at v dd ; ilim = gnd max1897 <1 5 a standby supply current (v cc ) (max1897, note 3) measured at v cc ; ilim = gnd 20 40 a shutdown supply current (v+) (max1897) measured at v+; v cc = v dd = 0 or 5v, shdn = gnd <1 5 a shutdown supply current (v dd ) (max1897, note 3) measured at v dd ; shdn = gnd <1 5 a shutdown supply current (v cc ) (max1897, note 3) measured at v cc ; shdn = gnd <1 5 a
max1887/max1897 quick-pwm slave controllers for multiphase, step-down supplies _______________________________________________________________________________________ 3 electrical characteristics (continued) (circuit of figure 1, v+ = 15v, v cc = v dd = 5v, v out = v comp = 1.2v, v cm+ = v cm- = v cs+ = v cs- = 1.2v, shdn = v cc (max1897), t a = 0 c to +85 c , unless otherwise noted. typical values are at t a = +25 c.) parameter symbol conditions min typ max units current sensing on-time adjustment range 0.42 < v comp < 2.8v, v out 0.7v -40 +40 % comp output current i comp sink and source 30 a max1887 -1.25 +1.25 current-balance offset (v cm+ - v cm- ) - (v cs+ - v cs- ), i comp = 0, -100mv (v cm+ - v cm- ) +100mv max1897 -1.25 +1.25 mv current-balance transconductance (v cm+ - v cm- ) - (v cs+ - v cs- ) = 25mv 1.2 ms current-sense, common-mode range cm+, cm-, cs+, cs- -0.2 +2.0 v current-sense input current cm+, cm-, cs+, cs- -1 +1 a v ilim = 0.5v 47.5 50.0 52.5 positive current-limit threshold v c_lim v cm+ - v cm- and v cs+ - v cs- v ilim = 1v 97.5 100.0 102.5 mv v ilim = 0.5v -80 -75 -70 negative current-limit threshold v cs+ - v cs- v ilim = 1v -160 -150 -140 mv ilim standby threshold voltage 0.2 0.3 v ilim input current -100 +100 na limit propagation delay t limit falling edge, 3mv over trip threshold 1.5 s limit output low voltage v ol ( limit ) i sink = 1ma 0.1 v limit leakage current i limit limit forced to 5.5v < 0.01 1.00 a fault protection v cc /v dd undervoltage lockout threshold (note 3) rising edge, hysteresis = 20mv, switching disabled below this level 3.45 3.85 v thermal shutdown threshold rising, hysteresis = 15 c (typ) 160 c gate drivers max1887 1.0 3.5 dh gate-driver on-resistance (note 4) r on ( d h ) v bst - v lx forced to 5v max1897 1.0 4.5 ? max1887 1.0 3.5 high state (pullup) max1897 1.0 4.5 max1887 0.4 1.0 dl gate-driver on-resistance (note 4) r on ( dl ) low state (pulldown) max1897 0.4 2.0 ? dh gate-driver source/sink current i dh dh forced to 2.5v, v bst - v lx forced to 5v 1.3 a dl gate-driver sink current i dl dl forced to 2.5v 4.0 a dl gate-driver source current i dl dl forced to 2.5v 1.3 a dl rising 35 dead time dh rising 26 ns
max1887/max1897 quick-pwm slave controllers for multiphase, step-down supplies 4 _______________________________________________________________________________________ electrical characteristics (circuit of figure 1, v+ = 15v, v cc = v dd = 5v, v out = v comp = 1.2v, v cm+ = v cm- = v cs+ = v cs- = 1.2v, shdn = v cc (max1897), t a = -40 c to +85 c , unless otherwise noted.) (note 5) parameter symbol conditions min typ max units pwm controller m ax 1887 ( 300kh z) , v + = 12v , v c om p = 1.2v 320 390 ton = gnd (550khz) 171 209 ton = open (300khz) 320 390 on time (note 3) t on max1897, v+ = 12v, v comp = 1.2v ton = v cc (200khz) 464 566 ns supply currents quiescent supply current (v+) i+ measured at v+; v ilim > 0.35v 40 a max1887 800 quiescent supply current (v dd ) (note 3) i dd measured at v dd ; v ilim > 0.35v max1897 5 a quiescent supply current (v cc ) (max1897, note 3) i cc measured at v cc ; v ilim > 0.35v 800 a standby supply current (v+) measured at v+; ilim = gnd 5 a max1887 40 standby supply current (v dd ) (note 3) measured at v dd ; ilim = gnd max1897 5 a standby supply current (v cc ) (max1897, note 3) measured at v cc ; ilim = gnd 40 a shutdown supply current (v+) (max1897) measured at v+; v cc = v dd = 0 or 5v, shdn = gnd 5a shutdown supply current (v dd ) (max1897, note 3) measured at v dd ; shdn = gnd 5 a electrical characteristics (continued) (circuit of figure 1, v+ = 15v, v cc = v dd = 5v, v out = v comp = 1.2v, v cm+ = v cm- = v cs+ = v cs- = 1.2v, shdn = v cc (max1897), t a = 0 c to +85 c , unless otherwise noted. typical values are at t a = +25 c.) parameter symbol conditions min typ max units logic logic input high voltage (max1897) v ih shdn , pol; v cc = 4.5v to 5.5v 2.4 v logic input low voltage (max1897) v il shdn , pol; v cc = 4.5v to 5.5v 0.8 v high 3.0 trig logic levels v trig 350mv hysteresis low 1.2 v logic high (v cc ; 200khz operation) v cc - 0.4 open (300khz operation) 1.5 3.1 ton logic levels (max1897) v ton logic low (gnd; 550khz operation) 0.5 v trig -1 +1 shdn (max1897) -1 +1 pol (max1897) -2 +1 logic input current ton = gnd or v dd (max1897) -2 +3 a
max1887/max1897 quick-pwm slave controllers for multiphase, step-down supplies _______________________________________________________________________________________ 5 electrical characteristics (continued) (circuit of figure 1, v+ = 15v, v cc = v dd = 5v, v out = v comp = 1.2v, v cm+ = v cm- = v cs+ = v cs- = 1.2v, shdn = v cc (max1897), t a = -40 c to +85 c , unless otherwise noted.) (note 5) parameter symbol conditions min typ max units shutdown supply current (v cc ) (max1897, note 3) measured at v cc ; shdn = gnd 5 a current sensing on-time adjustment range 0.42 < v comp < 2.8v, v out 0.7v -40 +40 % comp output current i comp sink and source 30 a max1887 -2.0 +2.0 current-balance offset (v cm+ - v cm- ) - (v cs+ - v cs- ), i comp = 0, -100mv (v cm+ - v cm- ) +100mv max1897 -2.0 +2.0 mv current-sense, common-mode range cm+, cm-, cs+, cs- -0.2 +2.0 v v ilim = 0.5v 47.5 52.5 positive current-limit threshold v c_lim v cm+ - v cm- and v cs+ - v cs- v ilim = 1v 97.5 102.5 mv v ilim = 0.5v -80 -70 negative current-limit threshold v cs+ - v cs- v ilim = 1v -160 -140 mv ilim standby threshold voltage 0.2 0.3 v fault protection v cc /v dd undervoltage lockout threshold (note 3) rising edge, hysteresis = 20mv, switching disabled below this level 3.45 3.85 v gate drivers max1887 3.5 dh gate-driver on-resistance (note 4) r on ( d h ) v bst - v lx forced to 5v max1897 4.5 ? max1887 3.5 high state (pullup) max1897 4.5 max1887 1.0 dl gate-driver on-resistance (note 4) r on ( dl ) low state (pulldown) max1897 2.0 ? logic high 3.0 trig logic levels v trig 350mv hysteresis low 1.2 v logic high (v cc ; 200khz operation) v cc - 0.4 open (300khz operation) 1.5 3.1 ton logic levels (max1897) v ton logic low (gnd; 550khz operation) 0.5 v note 1: on-time and off-time specifications are measured from 50% point to 50% point at the dh pin with lx = pgnd, v bst = 5v, and a 500pf capacitor from dh to lx to simulate external mosfet gate capacitance. actual in-circuit times may be different due to mosfet switching speeds. note 2: the trigger delay time, t trig , is measured from the time the trig pin transitions to time when the dl pin goes low. note 3: the 20-pin max1897 has a separate analog pwm supply voltage input (v cc ) and gate-driver supply input (v dd ). for the 16-pin max1887 device, the analog pwm supply voltage input and the gate-driver supply voltage input are internally connected and named v dd . note 4: production testing limitations due to package handling require relaxed maximum on-resistance specifications for the max1897 s qfn package. the max1887 and max1897 contain the same die, and the qfn package imposes no additional resistance in- circuit. note 5: specifications to -40 c are guaranteed by design and not production tested.
max1887/max1897 quick-pwm slave controllers for multiphase, step-down supplies 6 _______________________________________________________________________________________ 100 20 0.1 10 100 two-phase efficiency vs. load current (v out = 1.3v) 40 30 50 60 70 80 90 max1887 toc01 load current (a) efficiency (%) 1 v in = 8v v in = 5v v in = 12v v in = 20v 1.20 1.23 1.22 1.21 1.24 1.25 1.26 1.27 1.28 1.29 1.30 020 10 30 40 50 two-phase output voltage vs. load current (v out = 1.3v, v offset = -10mv) max1887 toc02 load current (a) output voltage (v) v in = 12.0v 100 20 0.1 10 100 two-phase efficiency vs. load current (v out = 1v) 40 30 50 60 70 80 90 max1887 toc03 load current (a) efficiency (%) 1 v in = 8v v in = 5v v in = 12v v in = 20v 0.92 0.93 0.94 0.95 0.96 0.97 0.98 0.99 1.00 0 10203040 two-phase output voltage vs. load current (v out = 1.0v, v offset = -10mv) max1887 toc04 output voltage (v) v in = 12.0v 0 10 20 30 40 50 60 70 80 010 5 15202530 no-load input current vs. input voltage max1887 toc05 input voltage (v) input current (ma) i in i bias = i dd + i cc master and slave 020 10 30 40 50 inductor current balance vs. load current max1887 toc06 load current (a) 0 0.2 0.4 0.6 0.8 1.0 inductor current offset: i lm - i ls (a) 0 0.2 0.1 0.4 0.3 0.6 0.5 0.7 010 5152025 inductor current balance vs. input voltage max1887 toc07 input voltage (v) i l(master) - i l(slave) (a) i out = no load i out = 40a 50 25 0 -25 -50 -0.5 0.5 0 1.0 1.5 2.0 offset voltage deviation vs. current-sense common-mode voltage max1887 toc08 v out (v) offset voltage deviation ( v) out = cm+ = cm- = cs+ = cs- -0.3 -0.1 -0.2 0.1 0 0.2 0.3 0 1.0 0.5 1.5 2.0 offset voltage deviation vs. compensation voltage max1887 toc09 v comp (v) offset voltage deviation (mv) out = cm+ = cm- = cs+ = cs- typical operating characteristics (circuit of figure 1, v+ = 12v, v cc = v dd = 5v, v out = 1.3v (zmode = gnd) and 1v (zmode = v cc ), shdn = v cc (max1897))
max1887/max1897 quick-pwm slave controllers for multiphase, step-down supplies _______________________________________________________________________________________ 7 0 20 40 60 80 100 120 140 160 0 0.5 1.0 1.5 positive current-limit threshold vs. ilim voltage max1887 toc13 v ilim (v) positive current limit (mv) master or slave standby mode -100 -40 -60 -80 -20 0 20 40 60 80 100 -150 -50 -100 0 50 100 150 compensation output current vs. current-sense voltage differential max1887 toc10 v cs+ - v cs- (v) icomp ( v) out = cm+ = cm- = cs- i comp = g m (v cs+ - v cs- ) 0 150 100 50 200 250 300 350 400 450 500 0 2.0 minimum trigger pulse width vs. overdrive voltage max1887 toc11 overdrive voltage (v) trigger pulse width (ns) 0.5 1.5 1.0 rising (out-of-phase) falling (in-phase) on-time triggered above the line 0 150 100 50 200 250 300 350 400 450 500 0 2.0 trigger propagation delay vs. overdrive voltage max1887 toc12 overdrive voltage (v) trigger propagation delay (ns) 0.5 1.5 1.0 rising (out-of-phase) falling (in-phase) typical operating characteristics (continued) (circuit of figure 1, v+ = 12v, v cc = v dd = 5v, v out = 1.3v (zmode = gnd) and 1v (zmode = v cc ), shdn = v cc (max1897))
max1887/max1897 quick-pwm slave controllers for multiphase, step-down supplies 8 _______________________________________________________________________________________ switching waveforms (out-of-phase) max1887 toc14 20a 10v 0 a 20mv/div b 5a/div c 10v/div 1 s/div a. output voltage, v out = 1.290v (no load), b. master/slave inductor currents c. master/slave lx waveforms, v in = 12.0v, i out = 40a, pol = v cc (max1897) typical operating characteristics (continued) (circuit of figure 1, v+ = 12v, v cc = v dd = 5v, v out = 1.3v (zmode = gnd) and 1v (zmode = v cc ), shdn = v cc (max1897)) switching waveforms (in-phase) max1887 toc15 20a 10v 0 a 20mv/div b 5a/div c 10v/div 1 s/div a. output voltage, v out = 1.290v (no load), b. master/slave inductor currents c. master/slave lx waveforms, v in = 12.0v, i out = 40a, pol = gnd (max1897) load transient (out-of-phase) max1887 toc16 5a 40a 0 1.282v 0 a 40a/div b 50mv/div c 10a/div d 10a/div 20 s/div a. load current, i out = 5a to 40a b. output voltage, v out = 1.290v (no load) c. slave inductor current d. master inductor current v in = 12.0v, pol = v cc (max1897) load transient (in-phase) max1887 toc17 a 40a/div 40a 5a 1.282v b 50mv/div c 10a/div d 10a/div 0 0 20 s/div a. load current, i out = 5a to 40a b. output voltage, v out = 1.290v (no load) c. slave inductor current d. master inductor current v in = 12.0v, pol = gnd (max1897)
max1887/max1897 quick-pwm slave controllers for multiphase, step-down supplies _______________________________________________________________________________________ 9 dynamic output voltage transition max1887 toc18 0 5.0v 0 1.3v 1.1v 0 a 5v/div b 200mv/div c 10a/div d 10a/div 40 s/div a. zmode = 0 to 5v b. output voltage, v out = 1.30v (zmode = gnd) or 1.10v (zmode = v cc ) c. slave inductor current d. master inductor current typical operating characteristics (continued) (circuit of figure 1, v+ = 12v, v cc = v dd = 5v, v out = 1.3v (zmode = gnd) and 1v (zmode = v cc ), shdn = v cc (max1897)) startup waveform (no load) max1887 toc19 5v 1v 0 0 0 0 a 5v/div b 1.0v/div d 10a/div c 10a/div 100 s/div a. master shutdown, v shdn = 0 to 5v b. output voltage, v out = 1.290v (no load) c. slave inductor current d. master inductor current max1887 toc20 5v 1v 0 0 0 0 a 5v/div b 1.0v/div d 10a/div c 10a/div 100 s/div a. master shutdown, v shdn = 5v to 0 b. output voltage, v out = 1.290v (no load) c. slave inductor current d. master inductor current shutdown waveform startup waveform (20a load) max1887 toc21 5v 0 0 0 0 a 5v/div b 1.0v/div d 10a/div c 10a/div 100 s/div a. master shutdown, v shdn = 0 to 5v b. output voltage, v out = 1.290v (no load) c. slave inductor current d. master inductor current r out = 65m ? (i out = 20a)
max1887/max1897 quick-pwm slave controllers for multiphase, step-down supplies 10 ______________________________________________________________________________________ pin description pin max1887 max1897 name description 1 19 ilim dual-mode current-limit adjustment and standby input. the current-limit threshold voltage is 1/10 the voltage seen at ilim (v ilim ) over a 400mv to 1.5v range. if v ilim drops below 250mv, the slave controller enters a low-power standby mode, forcing dl high and dh low. 2 20 trig trigger input. connect to the master controller s low-side gate driver. for the max1887, a rising edge triggers a single cycle. for the max1897, the trigger input s polarity is pin selectable. pol = v cc or floating triggers on the rising edge (out-of- phase operation), and pol = gnd triggers on the falling edge (in-phase operation). 3 1 cm+ master controller s positive current-sense input 4 2 cm- master controller s negative current-sense input 3 ton on-time selection control input. this is a three-level input used to determine the dh on time (see on-time control and active current balancing ). for the max1897, connect ton as follows for the indicated switching frequencies: gnd = 550khz floating = 300khz v cc = 200khz. for the max1887, the switching frequency is internally configured for 300khz operation. the slave controller s switching frequency should be selected to closely match the frequency of the master pwm controller. 5 4 cs- slave controller s negative current-sense input 6 5 cs+ slave controller s positive current-sense input 7 6 comp current balance compensation. connect a series resistor and capacitor between comp and out. see the current balance compensation section. 7 pol trig p ol ar i ty s el ect inp ut. c onnect p ol to v c c or fl oat to tr i g g er on the r i si ng ed g e of trig ( out- of- p hase op er ati on) . c onnect p ol to gn d to tr i g g er on the fal l i ng ed g e of trig ( i n- p hase op er ati on) . for the m ax 1887, p ol i s i nter nal l y connected to v c c . 8 8 gnd analog ground. connect the max1897 s exposed pad to analog ground. 9 9 pgnd power ground 10 10 dl low-side gate-driver output. dl swings from pgnd to v dd . dl is forced high when the max1897 enters standby or shutdown mode. 11 11 v dd supply voltage input for the dl gate driver. for the max1887, v dd also serves as the analog supply voltage input that powers the pwm core. connect to the system supply voltage (4.5v to 5.5v). bypass to pgnd with a 1f or greater ceramic capacitor, as close to the ic as possible. 12 v cc analog supply voltage input for pwm core. connect v cc to the system supply voltage (4.5v to 5.5v) through a series 10 ? resistor. bypass to gnd with a 0.22f or greater ceramic capacitor, as close to the max1897 as possible. 13 shdn active-low shutdown input. a logic low shuts down the max1897 slave controller, immediately pulling dl high and dh low. connect to v cc for normal operation.
max1887/max1897 quick-pwm slave controllers for multiphase, step-down supplies ______________________________________________________________________________________ 11 detailed description the max1887/max1897 step-down slave controllers are intended for low-voltage, high-current, multiphase dc-to-dc applications. the max1887/max1897 slave controllers can be combined with any of maxim s quick-pwm step-down controllers to form a multiphase dc-to-dc converter. when compared to single-phase operation, multiphase conversion lowers the peak inductor current by distributing the load current between parallel power paths. this simplifies compo- nent selection, power distribution to the load, and ther- mal layout. existing quick-pwm controllers, such as the max1718, function as the master controller, providing accurate output voltage regulation, fast transient response, and multiple fault protection features. synchronized to the master s low-side gate driver, the max1887/max1897 include a constant on-time con- troller, synchronous rectifier gate drive, active current balancing, and precision current-limit circuitry. on-time control and active current balancing the max1887/max1897 slave controller uses a con- stant on-time, voltage feed-forward architecture similar to maxim s quick-pwm controllers (figure 2). the con- trol algorithm is simple: the high-side switch on-time is determined solely by a one-shot whose period is inversely proportional to input voltage and directly pro- portional to the compensation voltage (v comp ). another one-shot sets a minimum off-time (130ns typi- cal). the on-time one-shot is triggered when the follow- ing conditions are satisfied: the slave detects a pin description (continued) pin max1887 max1897 name description 12 14 dh high-side gate-driver output. dh swings from lx to bst. 13 15 lx inductor connection. connect lx to the switched side of the inductor. lx serves as the lower supply rail for the dh high-side gate driver. 14 16 bst boost flying-capacitor connection. connect to an external capacitor and diode according to the standard application circuit (figure 1). an optional resistor in series with bst allows dh pullup current to be adjusted. 15 17 v+ battery voltage sense connection. connect v+ to the input power source. v+ is used only for pwm one-shot timing (see the on-time control and active current balancing section). 16 18 limit op en- d r ai n c ur r ent- li m i t outp ut. c onnect to the m aster contr ol l er s ad j ustab l e cur r ent- l i m i t i np ut ( ilim ) accor d i ng to the s tand ar d ap p l i cati on c i r cui t ( fi g ur e 1) . when the vol tag e acr oss the m aster contr ol l er s cur r ent- sense r esi stor ( v c m + - v c m - ) exceed s the cur r ent- l i m i t thr eshol d ( v ili m /10) , the m ax 1887/m ax 1897 p ul l s lim it l ow . table 1. component selection for standard applications component circuit of figure 1 output voltage 0.6v to 1.75v input voltage range 7v to 24v maximum load current 40a inductor (each phase) 0.6h sumida cdep134h-0r6 or panasonic etqp6f0r6bfa frequency 300khz (ton = float) high-side mosfet (n h , each phase) international rectifier (2) irf7811w low-side mosfet (n l , each phase) international rectifier (2) irf7822 or fairchild (3) fds7764a or input capacitor (c in ) (6) 10f 25v taiyo yuden tmk432bj106km or tdk c4532x5r1e106m output capacitor (c out ) (8) 270f 2v panasonic eefue0e271r current-sense resistors (r cs and r cm ) 1.5m ? voltage positioning gain (a vps ) 2
max1887/max1897 quick-pwm slave controllers for multiphase, step-down supplies 12 ______________________________________________________________________________________ transition on the trig input, the slave controller s inductor current is below its current-limit threshold, and the minimum off time has expired. for the max1887, a rising edge on the trigger input (trig) initiates a new cycle. for the max1897, the trigger input s polarity is selected by connecting pol to v cc (rising edge) or to gnd (falling edge). at the slave controller s core is the one-shot that sets the high-side switch s on-time. this fast, low-jitter one- shot adjusts the on-time in response to the input volt- age and the difference between the inductor currents in the master and the slave. two identical transconduc- tance amplifiers (g mm = g ms ) integrate the difference between the master and slave current-sense signals. the summed output is connected to comp, allowing adjustment of the integration time constant with a com- pensation capacitor connected at comp. the resulting compensation current and voltage may be determined by the following equations: where z comp is the impedance at the comp output. the pwm controller uses this integrated signal (v comp ) to set the slave controller s on time. when the master and slave current-sense signals (cm+ to cm- and cs+ to cs-) become unbalanced, the transconductance amplifiers adjust the slave controller s on time, allowing the slave inductor current to increase or decrease until the current-sense signals are properly balanced. = (master s on time) + (slave s on-time correction due to current imbalance) this control algorithm results in balanced inductor cur- rents with the slave switching frequency synchronized to the master. since the master operates at nearly con- stant frequency, the slave will as well. the benefits of a constant switching frequency are twofold: first, the fre- quency can be selected to avoid noise-sensitive regions of the spectrum; second, the inductor ripple- current operating point remains relatively constant, resulting in easy design methodology and predictable output voltage ripple. multiple phase switching effectively distributes the load among the external components, thereby improving the overall efficiency. distributing the load current between multiple phases lowers the peak inductor current by the tk v v k v v k iz v on comp in out in comp c in = ? ? ? ? ? ? = ? ? ? ? ? ? + ? ? ? ? ? ? igvvgvv vviz comp mm cm cm ms cs cs comp out comp comp = ()() =+ +? +? ?? ? table 2. component suppliers manufacturer phone [country code] website mosfets fairchild semiconductor [1] 888-522-5372 www.fairchildsemi.com international rectifier [1] 310-322-3331 www.irf.com siliconix [1] 203-268-6261 www.vishay.com capacitors kemet [1] 408-986-0424 www.kemet.com panasonic [1] 847-468-5624 www.panasonic.com sanyo [65] 281-3226 (singapore) [1] 408-749-9714 www.secc.co.jp taiyo yuden [03] 3667-3408 (japan) [1] 408-573-4150 www.t-yuden.com inductors coilcraft [1] 800-322-2645 www.coilcraft.com coiltronics [1] 561-752-5000 www.coiltronics.com sumida [1] 408-982-9660 www.sumida.com
max1887/max1897 quick-pwm slave controllers for multiphase, step-down supplies ______________________________________________________________________________________ 13 max1897 float (300khz) fb (master) ref (max1718) output v dd v cc limit pol ton comp gnd cm- cm+ cs- cs+ pgnd lx dh dl bst trig ds v+ shdn v cc d0 vgate d1 d2 v+ dm bst dh lx dl gnd fb neg pos time v dd d3 d4 s1 s0 sus mux control suspend inputs zmode cc ref ton ilim i lim max1718 on off float (300khz) c2 0.22 f to logic dac inputs c cc 47pf c ref 0.22 f r13 0 ? r8 53.6k ? r9 100k ? c5 470pf r10 34.8k ? 5v bias supply c3 1 f r7 10 ? c4 0.22 f c comp 470pf r comp 10k ? r11 113k ? r12 30.1k ? c6 100pf 5v bias supply c1 1 f max4322 skp/sdn ovp c bst(m) 0.1 f input 8v to 24v c in (6) 10 f 25v ceramic n h(m) n l(m) l m 0.6 f r cm 1.5m ? r5 510 ? 5v bias supply r fb 100 ? c fb 1000pf r time 62k ? r2 2.8k ? r1 301k ? r3 1k ? r4 1k ? c out (8) 270 f n h(s) n l(s) l s 0.6 h r cs 1.5m ? r13 200 ? r14 200 ? r15 200 ? r16 200 ? c7 4700pf c8 4700pf power ground analog ground (master) analog ground (slave) r6 10 ? c bst(s) 0.1 f figure 1. standard application circuit
max1887/max1897 quick-pwm slave controllers for multiphase, step-down supplies 14 ______________________________________________________________________________________ number of phases (1/ ) when compared to a single- phase converter. this significantly reduces the i 2 r loss- es across the inductor s series resistance, the mosfets on-resistance, and the board resistance. in-phase and out-of-phase operation multiphase systems can stagger the on times of each phase (out-of-phase operation) or simultaneously turn on all phases at the beginning of a new cycle (in-phase operation). when configured for out-of-phase operation, high input-to-output differential voltages (v in > v out ) max1887 (max1897)* q trig toff one-shot r s q q q trig edge detector q trig ton one-shot controller bias on-time compute positive cs limit negative cs limit 17r 2r r positive cm limit (v cc )* (ton)* v+ comp cs- cs+ cm+ cm- gms gmm limit (shdn)* bst dh lx dl pgnd trig (pol)* ilim gnd v dd figure 2. functional diagram
max1887/max1897 quick-pwm slave controllers for multiphase, step-down supplies ______________________________________________________________________________________ 15 prevent the on times from overlapping. therefore, the instantaneous input current peaks of each phase do not overlap, resulting in reduced input and output volt- age ripple and rms ripple current. this lowers the input and output capacitor requirements, which allows fewer or less expensive capacitors, and decreases shielding requirements for emi. when the on-times overlap at low input-to-output differential voltages (v in < v out ), the input currents of the overlapping phases may sum together, increasing the total input and output ripple voltage and rms ripple current. during in-phase operation, the input capacitors must support large, instantaneous input currents when the high-side mosfets turn on simultaneously, resulting in increased ripple voltage and current when compared to out-of-phase operation. the higher rms ripple cur- rent degrades efficiency due to power loss associated with the input capacitor s effective series resistance (esr). this typically requires a large number of low- esr input capacitors in parallel to meet input ripple current ratings or minimize esr-related losses. for the max1897, the polarity select input (pol) deter- mines whether rising edges (pol = v cc ) or falling edges (pol = gnd) trigger a new cycle. for low duty- cycle applications (duty factor < 50%), triggering on the rising edge of the master s low-side gate driver pre- vents both high-side mosfets from turning on at the same time. staggering the phases in this way lowers the input ripple current, thereby reducing the input capacitor requirements. for applications operating with approximately a 50% duty factor, out-of-phase opera- tion (pol = v cc ) causes the slave controller to com- plete an on-pulse coincident to the master controller determining when to initiate its next on-time. the noise generated when the slave controller turns off its high- side mosfet could compromise the master controller s feedback voltage and current-sense inputs, causing inaccurate decisions that lead to more jitter in the switching waveforms. under these conditions, trigger- ing off of the falling edge (pol = gnd) of the master s low-side gate driver forces the controllers to operate in- phase, improving the system s noise immunity. forced-pwm mode the max1887/max1897 controllers do not allow light- load pulse skipping. therefore, the master controller must be configured for forced-pwm operation. this pwm control scheme forces the low-side gate drive waveform to be the complement of the high-side gate drive waveform, allowing the inductor current to reverse. during negative load and downward output voltage transitions, forced-pwm operation allows the converter to sink current, rapidly pulling down the out- put voltage. another benefit of forced-pwm operation, the switching frequency remains relatively constant over the full load and input voltage ranges. 5v bias supply (v cc and v dd ) the max1887/max1897 require an external 5v bias supply in addition to the battery. typically this 5v bias supply is the notebook s 95% efficient 5v system sup- ply. keeping the bias supply external to the ic improves efficiency, eliminates power dissipation limita- tions, and removes the cost associated with the inter- nal, 5v linear regulator that would otherwise be needed to supply the pwm circuit and gate drivers. if stand- alone capability is needed, the 5v supply can be gen- erated with an external linear regulator. the 20-pin max1897 has a separate analog pwm sup- ply voltage input (v cc ) and gate-driver supply input (v dd ). for the 16-pin max1887 device, the analog pwm supply voltage input and the gate-driver supply voltage input are internally connected and named v dd . the battery input (v+) and 5v bias inputs (v cc and v dd ) can be tied together if the input source is a fixed 4.5v to 5.5v supply. the maximum current required from the 5v bias supply to power v cc (pwm controller) and v dd (gate-drive power) is: i bias = i cc + f sw (q g1 + q g2 ) = 10ma to 45ma (typ) where i cc is 525a typical, f sw is the switching frequency, and q g1 and q g2 are the mosfet data sheets total gate charge specification limits at v gs = 5v. shutdown (max1897 only) when shdn is driven low, the max1897 enters the micropower shutdown mode (table 3). shutdown immediately forces dl high, pulls dh low, and shuts down the pwm controller so the total supply current (i cc + i dd + i+) drops below 1a. when shdn is dri- ven high, the max1897 operates normally with the pwm controller enabled. table 3. approximate k-factor errors ton connection (max1897)* frequency setting (khz) k-factor (s) max k-factor error (%) v cc 200 5 10 float 300 3.3 10 gnd 550 1.8 10 * the max1887 is internally preset for 300khz operation.
max1887/max1897 quick-pwm slave controllers for multiphase, step-down supplies 16 ______________________________________________________________________________________ several quick-pwm converters that may be used as the master controller ramp down the output voltage at a controlled slew rate when shut down. when combined with these master controllers, the max1897 must not be deactivated until the output voltage is fully discharged. otherwise the slave s low side switch will turn on while the master is still attempting to regulate the output. in these applications, delay the shutdown input signal to the max1897 or permanently connect shdn to v cc and use standby mode to conserve power (see the standby mode section). standby mode the max1887/max1897 slave controllers enter a low- power standby mode when the ilim voltage (v ilim ) drops below 250mv (table 4). similar to shutdown mode, standby forces dl high, pulls dh low, and dis- ables the pwm controller to inhibit switching; however, the bias and fault protection circuitry remain active so the max1887/max1897 can continuously monitor the ilim input. when v ilim is driven above 250mv, the pwm controller is enabled. when the slave controller s current-limit voltage (v ilim ) is set through a resistive divider between the master controller s reference and gnd (see the current-limit circuitry section), the max1887/max1897 automatically enters low-power standby mode when the master con- troller shuts down. as the master s reference powers down, the resistive divider pulls ilim below 250mv, automatically activating the max1887/max1897 s low- power standby mode. current-limit circuitry when the master s inductor current exceeds its valley current limit, the master extends its off time by forcing dl high until the inductor current falls below the current- limit threshold. without a transition on the master s low- side gate driver, the slave cannot initiate a new on-time pulse so the slave s inductor current ramps down as well, maintaining the current balance. therefore, the slave s valley current limit only needs to protect the slave controller if the current-balance circuitry or the master current limit fails. the slave s ilim input voltage should be selected to properly adjust the master s cur- rent-limit threshold. dual-mode ilim input the current-limit input (ilim) features dual-mode opera- tion, serving as both the standby mode control input and the current-limit threshold adjustment. the slave controller enters a low-power standby mode when the ilim voltage (v ilim ) is pulled below 250mv. for ilim voltages from 400mv to 1.5v, the current-limit threshold voltage is precisely 0.1 ? v ilim . the current-limit volt- age may be accurately set with a resistive voltage- divider between the master controller s reference and gnd, allowing the max1887/max1897 to automatically enter the low-power standby mode. slave current limit the slave current-limit circuit employs a unique valley current-sensing algorithm. if the current-sense signal is above the current-limit threshold, the max1887/ max1897 will not initiate a new cycle (figure 3). the actual peak inductor current is greater than the current-limit threshold by an amount equal to the inductor ripple current. therefore, the exact current-limit characteristic and maxi- mum load capability are a function of the current-limit threshold, inductor value, and input voltage. the reward for this uncertainty is robust, overcurrent sensing. when combined with master controllers that contain output undervoltage protection circuits, this current-limit method is effective in almost every circumstance. table 4. operating mode truth table shdn ilim dl mode comments gnd x high shutdown micropower, shutdown mode (i cc +i dd < 1a typ). dl forced high, dh forced low, and the pwm controller disabled. v cc gnd (< 0.25v) high standby low-power, standby mode (i cc + i dd = 20a typ). dl forced high, dh forced low, and the pwm controller disabled. however, the bias and fault protection circuitry remain active so the max1887/max1897 can continuously monitor the ilim input. v cc high (> 0.25v) switching normal operation low-noise, fixed-frequency, pwm operation. the inductor current reverses with light loads. x = don t care
max1887/max1897 quick-pwm slave controllers for multiphase, step-down supplies ______________________________________________________________________________________ 17 there also is a negative current limit that prevents excessive reverse inductor currents when v out is sink- ing current. the negative current-limit threshold is set to approximately 150% of the positive current-limit thresh- old, and tracks the positive current limit when ilim is adjusted. the max1887/max1897 uses cs+ and cs- to differen- tially measure the current across an external sense resistor (r cs ) connected between the inductor and out- put capacitors. this configuration provides precise cur- rent balancing, current limiting, and voltage positioning with a 1% current-sense resistor. reducing the sense voltage decreases power dissipation but increases the relative measurement error. carefully observe the pc board layout guidelines to ensure that noise and dc errors don t corrupt the current- sense signals measured at cs+ and cs-. the ic should be mounted relatively close to the current-sense resistor with short, direct traces making a kelvin sense connec- tion. master current-limit adjustment (limit) the quick-pwm controllers that may be used as the master controller typically use the low-side mosfet s on-resistance as its current-sense element. this depen- dence on a loosely specified resistance with a large temperature coefficient causes inaccurate current limit- ing. as a result, high current-limit thresholds are need- ed to guarantee full-load operation under worst-case conditions. furthermore, the inaccurate current limit mandates the use of mosfets and inductors with excessively high current and power dissipation ratings. the slave includes a precision current-limit comparator that supplements the master s current-limit circuitry. the max1887/max1897 uses cm+ and cm- to differ- entially sense the master s inductor current across a current-sense resistor, providing a more accurate cur- rent limit. when the master s current-sense voltage exceeds the current limit set by ilim in the slave (see the dual-mode ilim input section), the open-drain cur- rent-limit comparator pulls limit low (figure 2). once the master triggers the current limit, a pulse-width mod- ulated output signal appears at limit. this signal is fil- tered and used to adjust the master s current-limit threshold. high-side, gate driver supply (bst) the gate drive voltage for the high-side, n-channel mosfet is generated by the flying capacitor boost cir- cuit (figure 4). the capacitor between bst and lx is alternately charged from the external 5v bias supply (v dd ) and placed in parallel with the high-side mosfet s gate-source terminals. on startup, the synchronous rectifier (low-side mosfet) forces lx to ground and charges the boost capacitor to 5v. on the second half of each cycle, the switch-mode power supply turns on the high-side mosfet by closing an internal switch between bst and dh. this provides the necessary gate-to-source voltage to turn on the high- side switch, an action that boosts the 5v gate drive signal above the system s main supply voltage (v+). inductor current i limit(valley) = i load(max) 2 - lir 2 () time 0 i peak i load i limit max1887 max1897 v+ bst dh lx (r bst )* d bst c bst c byp input (v in ) n h l ( )* optional?he resistor reduces the switching-node rise time. figure 3. valley current-limit threshold point figure 4. high-side gate driver boost circuitry
max1887/max1897 quick-pwm slave controllers for multiphase, step-down supplies 18 ______________________________________________________________________________________ mosfet gate drivers (dh, dl) the dh and dl drivers are optimized for driving moder- ately sized, high-side and larger, low-side power mosfets. this is consistent with the low duty factor seen in the notebook cpu environment, where a large v in - v out differential exists. an adaptive dead-time circuit monitors the dl output and prevents the high- side fet from turning on until dl is fully off. there must be a low resistance, low inductance path from the dl driver to the mosfet gate in order for the adaptive dead-time circuit to work properly. otherwise, the sense circuitry in the max1887/max1897 will interpret the mosfet gate as off while there is actually charge still left on the gate. use very short, wide traces (50mils to 100mils wide if the mosfet is 1 inch from the device). the dead time at the other edge (dh turning off) is determined by a fixed 35ns internal delay. the internal pulldown transistor that drives dl low is robust, with a 0.4 ? (typ) on-resistance. this helps pre- vent dl from being pulled up during the fast rise-time of the lx node, due to capacitive coupling from the drain to the gate of the low-side synchronous-rectifier mos- fet. however, for high-current applications, some com- binations of high- and low-side fets may cause excessive gate-drain coupling, leading to poor efficien- cy, emi, and shoot-through currents. this is often reme- died by adding a resistor less than 5 ? in series with bst, which increases the turn-on time of the high-side fet without degrading the turn-off time (figure 4). undervoltage lockout during startup, the v cc undervoltage lockout (uvlo) circuitry forces the dl gate driver high and the dh gate driver low, inhibiting switching until an adequate supply voltage is reached. once v cc rises above 3.75v, valid transitions detected at the trigger input initiate a corre- sponding on-time pulse (see the on-time control and active current balancing section). to ensure correct startup, the max1887/max1897 slave controller s undervoltage lockout voltage must be lower than the master controller s undervoltage lockout voltage. if the v cc voltage drops below 3.75v, it is assumed that there is not enough supply voltage to make valid deci- sions. to protect the output from overvoltage faults, dl is forced high in this mode to force the output to ground. this results in large negative inductor current and possibly small negative output voltages. if v cc is likely to drop in this fashion, the output can be clamped with a schottky diode to pgnd to reduce the negative excursion. thermal-fault protection the max1887/max1897 feature a thermal fault-protec- tion circuit. when the junction temperature rises above +160 c, a thermal sensor activates the standby logic, forces the dl low-side gate driver high, and pulls the dh high-side gate driver low. this quickly discharges the output capacitors, tripping the master controller s undervoltage lockout protection. the thermal sensor reactivates the slave controller after the junction tem- perature cools by 15 c. design procedure firmly establish the input voltage range and maximum load current before choosing a switching frequency and inductor operating point (ripple-current ratio). the primary design trade-off lies in choosing a good switch- ing frequency and inductor operating point, and the fol- lowing four factors dictate the rest of the design: input voltage range: the maximum value (v in(max) ) must accommodate the worst-case high ac adapter voltage. the minimum value (v in(min) ) must account for the lowest input voltage after drops due to connectors, fuses, and battery selector switches. if there is a choice at all, lower input voltages result in better efficiency. maximum load current: there are two values to con- sider. the peak load current (i load(max) ) determines the instantaneous component stresses and filtering requirements, and thus drives output capacitor selec- tion, inductor saturation rating, and the design of the current-limit circuit. the continuous load current (i load ) determines the thermal stresses and thus drives the selection of input capacitors, mosfets, and other criti- cal heat-contributing components. modern notebook cpus generally exhibit i load = i load(max) ? 80%. for multiphase systems, each phase supports a frac- tion of the load, depending on the current balancing. the highly accurate current sensing and balancing implemented by the max1887/max1897 slave con- troller evenly distributes the load among each phase: where is the number of phases. switching frequency: this choice determines the basic trade-off between size and efficiency. the opti- mal frequency is largely a function of maximum input voltage, due to mosfet switching losses that are pro- portional to frequency and v in 2 . the optimum frequen- cy also is a moving target, due to rapid improvements ii i load slave load master load () ( ) ==
max1887/max1897 quick-pwm slave controllers for multiphase, step-down supplies ______________________________________________________________________________________ 19 in mosfet technology that are making higher frequen- cies more practical. setting switch on time: the constant on-time control algorithm in the master results in a nearly constant switching frequency despite the lack of a fixed-frequen- cy clock generator. in the slave, the high-side switch on time is inversely proportional to v+ and directly propor- tional to the compensation voltage (v comp ): where k is internally preset to 3.3s for the max1887 or externally set by the ton pin-strap connection for the max1897 (table 3) set the nominal on time in the slave to match the on time in the master. an exact match is not necessary because the max1887/max1897 have wide t on adjust- ment ranges (40%). for example, if t on in the master is set to 250khz, the slave can be set to either 200khz or 300khz and still achieve good performance. care should be taken to ensure that the comp voltage remains within its output voltage range (0.42v to 2.80v). inductor operating point: this choice provides trade- offs between size vs. efficiency and transient response vs. output noise. low inductor values provide better transient response and smaller physical size, but also result in lower efficiency and higher output noise due to increased ripple current. the minimum practical induc- tor value is one that causes the circuit to operate at the edge of critical conduction (where the inductor current just touches zero with every cycle at maximum load). inductor values lower than this grant no further size- reduction benefit. the optimum operating point is usu- ally found between 20% and 50% ripple current. inductor selection the switching frequency and operating point (% ripple or lir) determine the inductor value as follows: where is the number of phases. example: = 2, i load = 40a, v in = 12v, v out = 1.3v, f sw = 300khz, 30% ripple current or lir = 0.3: find a low-loss inductor having the lowest possible dc resistance that fits in the allotted dimensions. ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at 200khz. the core must be large enough not to saturate at the peak inductor current (i peak ): where is the number of phases. transient response the inductor ripple current affects transient-response performance, especially at low v in - v out differentials. low inductor values allow the inductor current to slew faster, replenishing charge removed from the output fil- ter capacitors by a sudden load step. the amount of output sag also is a function of the maximum duty fac- tor, which can be calculated from the on time and mini- mum off time: where t off(min) is the minimum off time (see the electrical characteristics section), is the number of phases, and k is from table 3. the amount of overshoot due to stored inductor energy can be calculated as: setting the current limits the master and slave current-limit thresholds must be great enough to support the maximum load current, even under worst-case operating conditions. since the master s current limit determines the maximum load (see the current-limit circuitry section), the procedure for setting the current limit is sequential. first, the mas- ter s current limit is set based on the operating condi- tions and the characteristics of the low-side mosfets. then the slave controller is configured to adjust the master s current-limit threshold based on the precise current-sense resistor value and variation in the mos- fet characteristics. finally, the resulting valley current limit for the slave s inductor occurs above the master s v il cv soar load max out out () ? () 2 2 v li vk v t cv vv k v t sag load max out in off min out out in out in off min = () ? ? ? ? ? ? + ? ? ? ? ? ? ? ? () ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? () () () 2 2 ii lir peak load max = + ? ? ? ? ? ? () 2 2 l vx v v x v x khz x a x h = () = ? 13 12 13 2 12 300 40 0 3 064 .. . . l vxvv x v xf xi xlir out in out in sw load max = () ? () tk v v on comp in = ? ? ? ? ? ?
max1887/max1897 quick-pwm slave controllers for multiphase, step-down supplies 20 ______________________________________________________________________________________ current-limit threshold. this is acceptable since the slave s inductor current limit only serves as a fail-safe in case the master and slave inductor currents become significantly unbalanced during a transient. the basic operating conditions are determined using the same calculations provided in any quick-pwm reg- ulator data sheet. the valley of the inductor current (i limit(valley) ) occurs at i load(max) divided by the number of phases minus half of the peak-to-peak inductor current: where the peak-to-peak inductor current may be deter- mined by the following equation: the master s high current-limit threshold must be set high enough to support the maximum load current, even when the master s current-limit threshold is at its minimum tolerance value, as described in the master controller s data sheet. most quick-pwm controllers that may be chosen as the master controller use the low-side mosfet s on-resistance to sense the inductor current. in these applications, the worst-case maximum value for r ds(on) plus some margin for the rise in r ds(on) over temperature must be used to determine the master s current-limit threshold. a good general rule is to allow 0.5% additional resistance for each c of temperature rise. set the master current-limit threshold to support the maximum load current for the maximum r ds(on) and minimum current-limit tolerance value: v ithm(high) (i limit(valley) )r ds(on)(max) where v ithm , the master s current-limit threshold, is typ- ically 1/10th the voltage seen at the master s ilim input (v ithm = 0.1 x v lim(master) , see the master con- troller s data sheet). connect a resistive voltage-divider from the master controller s internal reference to gnd, with the master s ilim input connected to the center tap (figure 5). use 1% tolerance resistors in the divider with 10a to 20a dc bias current to prevent significant errors due to the ilim pin s input current: configure the slave controller so its limit output begins to roll off after the master current-limit threshold occurs: where v iths , the slave s current-limit threshold, is pre- cisely one-tenth the voltage seen at the slave s ilim input (v iths = 0.1 ? v ilim(slave) ). connect a second resistive voltage-divider from the master controller s internal reference to gnd, with the slave s ilim input connected to the center tap (figure 5). the external adjustment range of 400mv to 1.5v corresponds to a vr v r i iths cm ithm high ds on max inductor + ? ? ? ? ? ? () ()( ) ? v a r v a r v v r ilim master b ilim master a ref master ilim master b () () () () 20 10 1 ? ? = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? i vvv vf l inductor out in out in sw = () ? i i i limit valley load max inductor () () ? ? ? ? ? ? ? ? ? ? ? ? ? ? 2 max1718 max1887 max1897 slave controller ilim limit master controller ref ilim r c r limit c limit r d r a r b c ref figure 5. setting the adjustable current limits v r rr v v rr rrr v v r rr v ithm high b ab ref ithm high b limit a b limit ref iths d cd ref () () // // = + ? ? ? ? ? ? = + () ? ? ? ? ? ? = + ? ? ? ? ? ? 1 10 1 10 1 10
max1887/max1897 quick-pwm slave controllers for multiphase, step-down supplies ______________________________________________________________________________________ 21 current-limit threshold of 40mv to 150mv. use 1% toler- ance resistors in the divider with 10a to 20a dc bias current to prevent significant errors due to the ilim pin s input current. reducing the current-limit threshold voltage lowers the sense resistor s power dissipation, but this also increases the relative measurement error: now, set the current-limit adjustment ratio (a adj = v ithm(high) /v ithm(low) ) greater than the maximum to minimum on-resistance ratio (a rds = r ds(on)(max) / r ds(on)(min) ): increasing a adj improves the master s current-limit accuracy but also increases the current limit s noise sensitivity. therefore, r limit may be selected using the following equation: finally, verify that the total load on the master s refer- ence does not exceed 50a: current limit design example for the typical application circuit shown in figure 1: v in = 12v, v out = 1.3v, f sw = 300khz, = 2, i load(max) = 50a, l = 0.6h, r ds(on)(max) = 6m ? , r ds(on)(min ) = 3m ? 1) determine the peak-to-peak inductor current and the valley current limit: 2) determine the master s current-limit threshold from the valley current limit and low-side mosfets max- imum on-resistance over temperature: v ith(master) 21.8a ? 6m ? = 130mv now select the resistive-divider values (r a and r b in figure 5) to set the appropriate voltage at the master s ilim input: selecting r b = 100k ? 1% provides the following value for r a : 3) determine the slave s current-limit threshold: select the resistive-divider values (r c and r d in figure 5) to set the appropriate voltage at the slave s ilim input: selecting r d = 30.1k ? 1% provides the following value for r a : 4) determine r limit (figure 5) from the above equation: 5) finally, verify that that the total bias currents do not exceed the 50a maximum load of the master s ref- erence: i v kkk v kk a bias total () // . . = + () ? ? ? ? ? ? + + ? ? ? ? ? ? = 2 54 100 34 8 2 30 1 113 36 ??? ?? r kkxm mm k limit () ? 53 6 100 3 63 35 .// ??? ?? ? r v xmv xk k c =? ? ? ? ? ? ? 2 10 42 1 30 1 113 . ?? r xmv a to xmv a kto k d = ? ? ? ? ? ? ? ? ? ? ? ? = 10 42 20 10 42 10 21 42 ? ?? vmx mv m amv iths + ? ? ? ? ? ? 15 130 6 64 42 .. ? ? r v xmv xk k a = ? ? ? ? ? ? ? 2 10 130 1 100 54 ?? r xmv a to xmv a kto k b = ? ? ? ? ? ? ? ? ? ? ? ? = 10 130 20 10 130 10 65 130 ? ?? ? i vx v v v x khz x h a i a xa a inductor limit valley = () = = ? ? ? ? ? ? ? ? ? ? ? ? = ? ? 13 12 13 12 300 0 6 64 50 2 1 2 6 4 21 8 .. . . .. () i v rrr v rr a bias total ref a b limit ref cd () // = + () ? ? ? ? ? ? + + ? ? ? ? ? ? 50 r rrr rr limit a b ds on min ds on max ds on min () ? // ()( ) ()( ) ()( ) // ()( ) ()( ) aa rr r r r adj ros ab limit ds on max ds on min + ? ? ? ? ? ? 1 v a r v a r v v r ilim slave d ilim slave c ref master ilim slave d () () () () 20 10 1 ? ? = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
max1887/max1897 quick-pwm slave controllers for multiphase, step-down supplies 22 ______________________________________________________________________________________ when unadjusted, the on-resistance variation of the low-side mosfets results in a maximum current-limit variation ( ? i limit ) determined by the following equation: where a rds = r ds(on)(max) /r ds(on)(min) . using the max1887/max1897 to adjust the master s current-limit threshold results in a maximum current-limit variation less than the peak-to-peak inductor current: adjusted ? i limit ? i inductor as shown in figure 6, the resulting current-limit varia- tion of the master is dramatically reduced. for the above example, this control scheme reduces the cur- rent-limit variation from 21.7a (unadjusted) to less than 6.4a (adjusted). output capacitor selection the output filter capacitor must have low enough effec- tive series resistance (esr) to meet output ripple and load-transient requirements, yet have high enough esr to satisfy stability requirements. in cpu v core converters and other applications where the output is subject to large load transients, the output capacitor selection typically depends on how much esr is needed to prevent the output from dipping too low under a load transient. ignoring the sag due to finite capacitance: r v i esr step load max ? () unadjusted i v a r limit ithm high rds ds on max ?= ? ? ? ? ? ? ? () ()( ) 1 0 20 40 60 80 100 120 140 160 0 1020304050 slave current-limit voltages vs. average inductor current average inductor current (a) voltage (mv) i adj(min) = i peak = v iths r cm v ithm(high) v ithm(low) v iths ? i adj - ? i inductor = r cm i lm(peak) = r cs i ls(peak) r cm i lm(valley) = r cs i ls(valley) v out (v in - v out ) v in f sw l [] 0 20 40 60 80 100 120 140 160 0 1020304050 master current-limit voltages vs. average inductor current average inductor current (a) voltage (mv) v ithm(high) v ithm(low) adjusted ? i limit ? i inductor unadjusted ? i limit ? i limit = v ithm(high) r ds(on)(min) = l lm(valley) r ds(on)(min) = l lm(valley) master controller slave controller a rds - 1 r ds(on)(max) () figure 6. master/slave current-limit thresholds
max1887/max1897 quick-pwm slave controllers for multiphase, step-down supplies ______________________________________________________________________________________ 23 in non-cpu applications, the output capacitor selection often depends on how much esr is needed to maintain an acceptable level of output ripple voltage. the output ripple voltage of a step-down controller equals the total inductor ripple current multiplied by the output capaci- tor s esr. when operating multiphase systems out-of- phase, the peak inductor currents of each phase are staggered, resulting in lower output ripple voltage by reducing the total inductor ripple current. for out-of- phase operation, the maximum esr to meet ripple requirements is: this equation may be rewritten as the single phase rip- ple current minus a correction due to the additional phases: where t trig is the max1887/max1897 s trigger propa- gation delay, is the number of phases, and k is from table 3. when operating the max1897 in-phase (pol = gnd), the high-side mosfets turn on together, so the output capacitors must simultaneously support the combined inductor ripple currents of each phase. for in-phase operation, the maximum esr to meet ripple requirements is: the actual capacitance value required relates to the physical size needed to achieve low esr, as well as to the chemistry of the capacitor technology. thus, the capacitor is usually selected by esr and voltage rating rather than by capacitance value (this is true of tanta- lums, os-cons, and other electrolytics). when using low-capacity filter capacitors such as ceramic or polymer types, capacitor size is usually determined by the capacity needed to prevent v sag and v soar from causing problems during load tran- sients. generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the ris- ing load edge is no longer a problem (see the v sag and v soar equations in the transient response section). output capacitor stability considerations for quick-pwm controllers, stability is determined by the value of the esr zero relative to the switching fre- quency. the boundary of instability is given by the fol- lowing equation: where: for a standard 300khz application, the esr zero fre- quency must be well below 95khz, preferably below 50khz. tantalum, sanyo poscap, and panasonic sp capacitors in wide-spread use at the time of publication have typical esr zero frequencies below 30khz. in the standard application used for inductor selection, the esr needed to support a 30mv p-p ripple is 30mv/(40a x 0.3) = 2.5m ? . eight 270f/2v panasonic sp capaci- tors in parallel provide 1.9m ? (max) esr. their typical combined esr results in a zero at 39khz. don t put high-value ceramic capacitors directly across the output without taking precautions to ensure stability. ceramic capacitors have a high esr zero frequency and may cause erratic, unstable operation. however, it s easy to add enough series resistance by placing the capacitors a couple of centimeters downstream from the junction of the inductor and fb pin. unstable operation manifests itself in two related but distinctly different ways: double-pulsing and feedback loop instability. double-pulsing occurs due to noise on the output or because the esr is so low that there isn t enough voltage ramp in the output voltage signal. this fools the error comparator into triggering a new cycle immediately after the minimum off-time period has expired. double-pulsing is more annoying than harmful, resulting in nothing worse than increased output ripple. however, it can indicate the possible presence of loop instability due to insufficient esr. loop instability can result in oscillations at the output after line or load steps. such perturbations are usually damped, but can cause the output voltage to rise above or fall below the tolerance limits. the easiest method for checking stability is to apply a very fast zero-to-max load transient and carefully observe the output voltage ripple envelope for over- shoot and ringing. it can help to simultaneously monitor the switching waveforms (v lx and/or i inductor ). don t allow more than one cycle of ringing after the initial step-response under/overshoot. f f f rc esr sw esr esr out = 1 2 r v i lir v fl v v vv esr ripple load max ripple sw out in in out = ? ? ? ? ? ? ? ? ? ? ? ? () ? () r v i lir v l tt esr ripple load max out on trig () ? ? ? ? ? ? + () ? ? ? ? ? ? ?? () ? 1 r v l vv f v v vt esr ripple in out sw out in out trig ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? () ? ? ? ? ? ? ? ? ? ?? ? 1
max1887/max1897 input capacitor selection the input capacitor must meet the ripple current requirement (i rms ) imposed by the switching currents. the max1887/max1897 multiphase slave controllers operate out-of-phase (max1897 pol = v cc or float), staggering the turn-on times of each phase. this mini- mizes the input ripple current by dividing the load cur- rent among independent phases: for out-of-phase operation. when operating the max1897 in-phase (pol = gnd), the high-side mosfets turn on simultaneously, so input capacitors must support the combined input rip- ple currents of each phase: for in-phase operation. for most applications, nontantalum chemistries (ceram- ic, aluminum, or os-con) are preferred because of their resistance to inrush surge currents typical of sys- tems with a mechanical switch or connector in series with the input. if the max1887/max1897 is operated as the second stage of a two-stage power-conversion sys- tem, tantalum input capacitors are acceptable. in either configuration, choose an input capacitor that exhibits less than +10 c temperature rise at the rms input cur- rent for optimal circuit longevity. power mosfet selection most of the following mosfet guidelines focus on the challenge of obtaining high load-current capability when using high-voltage (>20v) ac adapters. low-cur- rent applications usually require less attention. the high-side mosfet (n h ) must be able to dissipate the resistive losses plus the switching losses at both v in(min) and v in(max) . calculate both of these sums. ideally, the losses at v in(min) should be roughly equal to losses at v in(max) , with lower losses in between. if the losses at v in(min) are significantly higher than the losses at v in(max) , consider increasing the size of n h . conversely, if the losses at v in(max) are significantly higher than the losses at v in(min) , consider reducing the size of n h . if v in does not vary over a wide range, the minimum power dissipation occurs where the resis- tive losses equal the switching losses. choose a low-side mosfet that has the lowest possi- ble on-resistance (r ds(on) ), comes in a moderate- sized package (i.e., one or two so-8s, dpak or d 2 pak), and is reasonably priced. make sure that the dl gate driver can supply sufficient current to support the gate charge and the current injected into the para- sitic gate-to-drain capacitor caused by the high-side mosfet turning on; otherwise, cross-conduction prob- lems may occur. mosfet power dissipation worst-case conduction losses occur at the duty factor extremes. for the high-side mosfet (n h ), the worst- case power dissipation due to resistance occurs at the minimum input voltage: generally, a small high-side mosfet is desired to reduce switching losses at high input voltages. however, the r ds(on) required to stay within package power-dissipation often limits how small the mosfet can be. again, the optimum occurs when the switching losses equal the conduction (r ds(on) ) losses. high- side switching losses don t usually become an issue until the input is greater than approximately 15v. calculating the power dissipation of the high-side mosfet (n h ) due to switching losses is difficult since it must allow for difficult quantifying factors that influence the turn-on and turn-off times. these factors include the internal gate resistance, gate charge, threshold volt- age, source inductance, and pc board layout charac- teristics. the following switching-loss calculation provides only a very rough estimate and is no substi- tute for breadboard evaluation, preferably including verification using a thermocouple mounted on n h : where c rss is the reverse transfer capacitance of n h and i gate is the peak gate-drive source/sink current (1a typ). switching losses in the high-side mosfet can become an insidious heat problem when maximum ac adapter voltages are applied, due to the squared term in the c ? v in 2 ? f sw switching-loss equation. if the high-side mosfet chosen for adequate r ds(on) at low battery voltages becomes extraordinarily hot when biased from pd n switching vcfi i h in max rss sw load gate () () = () 2 pd n sistive v v i r h out in load ds on (re ) () = ? ? ? ? ? ? ? ? ? ? ? ? 2 ii vvv v rms load out in out in = () ? ? ? ? ? ? ? ? ? i i vvv v rms load out in out in = ? ? ? ? ? ? () ? ? ? ? ? ? ? ? ? quick-pwm slave controllers for multiphase, step-down supplies 24 ______________________________________________________________________________________
v in(max) , consider choosing another mosfet with lower parasitic capacitance. for the low-side mosfet (n l ), the worst-case power dissipation always occurs at maximum input voltage: the worst case for mosfet power dissipation occurs under heavy overloads that are greater than i load(max) but are not quite high enough to exceed the current limit and cause the fault latch to trip. to pro- tect against this possibility, overdesign the circuit to tolerate: where i valley(max) is the maximum valley current allowed by the current-limit circuit, including threshold tolerance and on-resistance variation. the mosfets must have a good-sized heatsink to handle the over- load power dissipation. choose a schottky diode (d1) with a forward voltage low enough to prevent the low-side mosfet body diode from turning on during the dead time. as a gen- eral rule, select a diode with a dc current rating equal to 1/(3 ) of the load current. this diode is optional and can be removed if efficiency is not critical. current balance compensation (comp) the current balance compensation capacitor (c comp ) integrates the difference of the master and slave cur- rent-sense signals, while the compensation resistor improves transient response by increasing the phase margin. this allows the user to optimize the dynamics of the current balance loop. excessively large capacitor values increase the integration time constant, resulting in larger current differences between the phases during transients. excessively small capacitor values allow the current loop to respond cycle by cycle but can result in small dc current variations between the phases. likewise, excessively large series resistance can also cause dc current variations between the phases. small series resistance reduces the phase margin, resulting in marginal stability in the current balance loop. for most applications, a 470pf capacitor and 10k ? series resistor from comp to the converter s output voltage works well. the compensation network can be tied to v out to include the feed-forward term due to the master s on time (see the on-time control and active current balancing section). to reduce noise pick-up in applica- tions that have a widely distributed layout, it is some- times helpful to connect the compensation network to quiet analog ground rather than v out . applications information voltage positioning and effective efficiency powering new mobile processors requires careful attention to detail to reduce cost, size, and power dissi- pation. as cpus became more power hungry, it was recognized that even the fastest dc-dc converters were inadequate to handle the transient power require- ments. after a load transient, the output instantly changes by esr cout ? ? i load . conventional dc-dc converters respond by regulating the output voltage back to its nominal state after the load transient occurs (figure 7). however, the cpu only requires that the out- put voltage remain above a specified minimum value. dynamically positioning the output voltage to this lower limit allows the use of fewer output capacitors and reduces power consumption under load. for a conventional (nonvoltage-positioned) circuit, the total voltage change is: v p-p 1 = 2 ? (esr cout ? ? i load ) + v sag + v soar where v sag and v soar are defined in figure 8. setting the converter to regulate at a lower voltage when under load allows a larger voltage step when the output cur- rent suddenly decreases (figure 7). so the total voltage change for a voltage-positioned circuit is: v p-p 2 = (esr cout ? ? i load ) + v sag + v soar where v sag and v soar are defined in the design procedure section. since the amplitudes are the same for both circuits (v p-p 1 = v p-p 2), the voltage-positioned circuit tolerates twice the esr. since the esr specifica- tion is achieved by paralleling several capacitors, fewer units are needed for the voltage-positioned circuit. an additional benefit of voltage positioning is reduced power consumption at high load currents. since the output voltage is lower under load, the cpu draws less current. the result is lower power dissipation in the cpu, although some extra power is dissipated in r sense . for a nominal 1.6v, 22a output (r load = 72.7m ? ), reducing the output voltage 2.9% gives an output voltage of 1.55v and an output current of 21.3a. given these values, cpu power consumption is reduced from 35.2w to 33.03w. the additional power consumption of r sense is: ii i lir load valley max load max =+ ? ? ? ? ? ? () () 2 pd n sistive v v i r l out in max load ds on (re ) () () = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 2 max1887/max1897 quick-pwm slave controllers for multiphase, step-down supplies ______________________________________________________________________________________ 25
max1887/max1897 50mv x 21.3a = 1.06w, which results in an overall power savings of: 35.2w - (33.03w + 1.06w) = 1.10w. in effect, 2.2w of cpu dissipation is saved and the power supply dissipates much of the savings, but both the net savings and the transfer of dissipation away from the hot cpu are beneficial. effective efficiency is defined as the efficiency required of a nonvoltage-posi- tioned circuit to equal the total dissipation of a voltage- positioned circuit for a given cpu operating condition. calculate effective efficiency as follows: 1) start with the efficiency data for the positioned cir- cuit (v in , i in , v out , i out ). 2) model the load resistance for each data point: r load = v out / i out 3) calculate the output current that would exist for each r load data point in a nonpositioned application: i np = v np / r load where v np = 1.6v (in this example). 4) calculate effective efficiency as: effective efficiency = (v np ? i np ) / (v in ? i in ) = cal- culated nonpositioned power output divided by the measured voltage-positioned power input. 5) plot the efficiency data point at the nonpositioned current, i np . the effective efficiency of voltage-positioned circuits is shown in the typical operating characteristics . one-stage (battery input) versus two-stage (5v input) applications the max1887/max1897 can be used with a direct bat- tery connection (one stage) or can obtain power from a regulated 5v supply (two-stage). each approach has advantages, and careful consideration should go into the selection of the final design. the one-stage approach offers smaller total inductor size and fewer capacitors overall due to the reduced demands on the 5v supply. due to the high input volt- age, the one-stage approach requires lower dc input currents, reducing input connection/bus requirements and power dissipation due to input resistance. the transient response of the single stage is better due to the ability to ramp the inductor current faster. the total efficiency of a single stage is better than the two-stage approach. the two-stage approach allows flexible placement due to smaller circuit size and reduced local power dissipa- tion. the power supply can be placed closer to the cpu for better regulation and lower i 2 r losses from pc board traces. although the two-stage design has slow- er transient response than the single stage, this can be offset by the use of a voltage-positioned converter. quick-pwm slave controllers for multiphase, step-down supplies 26 ______________________________________________________________________________________ v out esr voltage step (i step x r esr ) capacitive soar (dv/dt = i out /c out ) recovery capacitive sag (dv/dt = i out /c out ) i load figure 8. transient response regions b 1.4v 1.4v a a. conventional converter (50mv/div) b. voltage-positioned output (50mv/div) voltage positioning the output figure 7. voltage positioning the output
ceramic output capacitor applications ceramic capacitors have advantages and disadvan- tages. they have ultra-low esr and are noncom- bustible, relatively small, and nonpolarized. however, they are also expensive and brittle, and their ultra-low esr characteristic can result in excessively high esr zero frequencies. in addition, their relatively low capac- itance value can cause output overshoot when step- ping from full-load to no-load conditions, unless a small inductor value is used (high switching frequency), or there are some bulk tantalum or electrolytic capacitors in parallel to absorb the stored inductor energy. in some cases, there may be no room for electrolytics, creating a need for a dc-dc design that uses nothing but ceramics. the max1887/max1897 can take full advantage of the small size and low esr of ceramic output capacitors in a voltage-positioned circuit. the addition of the posi- tioning resistor increases the ripple at fb, lowering the effective esr zero frequency of the ceramic output capacitor. output overshoot (v soar ) determines the minimum output capacitance requirement (see the output capacitor selection section). often the switching fre- quency is increased to 550khz, and the inductor value is reduced to minimize the energy transferred from inductor to capacitor during load-step recovery. the efficiency penalty for operating at 550khz is about 3% when compared to the 300khz circuit, primarily due to the high-side mosfet switching losses. pc board layout guidelines careful pc board layout is critical to achieve low switching losses and clean, stable operation. the switching power stage requires particular attention (figure 9). if possible, mount all of the power compo- nents on the top side of the board with their ground ter- minals flush against one another. follow these guidelines for good pc board layout: 1) keep the high-current paths short, especially at the ground terminals. this is essential for stable, jitter- free operation 2) connect all analog grounds to a separate solid copper plane, which connects to the gnd pin of the max1887/max1897. this includes the v cc bypass capacitor, comp components, and the resistive-divider connected to ilim. 3) the master controller also should have a separate analog ground. return the appropriate noise sensi- tive components to this plane. since the reference in the master is sometimes connected to the slave, it may be necessary to couple the analog ground in the master to the analog ground in the slave to pre- vent ground offsets. a low value ( 10 ? ) resistor is sufficient to link the two grounds. 4) keep the power traces and load connections short. this is essential for high efficiency. the use of thick copper pc boards (2oz vs. 1oz) can enhance full-load efficiency by 1% or more. correctly routing pc board traces is a difficult task that must be approached in terms of fractions of centimeters, where a single m ? of excess trace resistance causes a measurable effi- ciency penalty. 5) keep the high-current gate-driver traces (dl, dh, lx, and bst) short and wide to minimize trace resistance and inductance. this is essential for high-power mosfets that require low-impedance gate drivers to avoid shoot-through currents. 6) cs+, cs-, cm+, and cm- connections for current limiting and balancing must be made using kelvin sense connections to guarantee the current-sense accuracy. 7) when trade-offs in trace lengths must be made, it s preferable to allow the inductor charging path to be made longer than the discharge path. for example, it s better to allow some extra distance between the input capacitors and the high-side mosfet than to allow distance between the inductor and the low-side mosfet or between the inductor and the output filter capacitor. 8) route high-speed switching nodes away from sen- sitive analog areas (comp, ilim). make all pin- strap control input connections ( shdn , ilim, pol) to analog ground or v cc rather than power ground or v dd . layout procedure 1) place the power components first, with ground termi- nals adjacent (low-side mosfet source, c in , c out , and d1 anode). if possible, make all these connec- tions on the top layer with wide, copper-filled areas. 2) mount the controller ic adjacent to the low-side mosfet. the dl gate trace must be short and wide (50mils to 100mils wide if the mosfet is 1 inch from the controller ic). 3) group the gate-drive components (bst diode and capacitor, v dd bypass capacitor) together near the controller ic. 4) make the dc-dc controller ground connections as shown in figure 1. this diagram can be viewed as having four separate ground planes: input/output ground, where all the high-power components go; the power ground plane, where the pgnd pin and max1887/max1897 quick-pwm slave controllers for multiphase, step-down supplies ______________________________________________________________________________________ 27
max1887/max1897 quick-pwm slave controllers for multiphase, step-down supplies 28 ______________________________________________________________________________________ power ground lm dm ls c out c out c out c out c out c out c out c out via to power ground output slave master via to cs- via to cs+ via to cm- via to cm+ and fb max1718 (master) connect gnd and pgnd beneath the controller at one point only as shown via to power ground max1897 (slave) connect the exposed pad to gnd c in c in c in c in c in c in c in c in input (v+) slave master top layer bottom layer 10 ? power ground ds figure 9. power-stage pc board layout example
v dd bypass capacitor go; the master s analog ground plane where sensitive analog components, the master s gnd pin and v cc bypass capacitor go; and the slave s analog ground plane where the slave s gnd pin, and v cc bypass capacitor go. the master s gnd plane must meet the pgnd plane only at a single point directly beneath the ic. similarly, the slave s gnd plane must meet the pgnd plane only at a single point directly beneath the ic. the respective master and slave ground planes should connect to the high-power output ground with a short metal trace from pgnd to the source of the low-side mosfet (the middle of the star ground). this point must also be very close to the output capacitor ground terminal. 5) connect the output power planes (v core and sys- tem ground planes) directly to the output filter capacitor positive and negative terminals with multi- ple vias. place the entire dc-dc converter circuit as close to the cpu as is practical. chip information transistor count: 1422 process: bicmos max1887/max1897 quick-pwm slave controllers for multiphase, step-down supplies ______________________________________________________________________________________ 29 max1887 (max1897)* ref (master) float (300khz) ilim (master) fb (master) ( )* max1897 pins only master low-side gate driver master current sense resistor output input 5v bias supply v dd (v cc )* (pol)* ilim (ton)* limit comp gnd trig cm- cm+ cs- cs+ pgnd dl dh bst v+ shdn lx typical operating circuit pin configurations (continued) 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 ilim limit v+ bst lx dh v dd dl pgnd top view max1887 qsop trig cm+ cs+ cm- cs- comp gnd
max1887/max1897 quick-pwm slave controllers for multiphase, step-down supplies 30 ______________________________________________________________________________________ qsop.eps package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)
max1887/max1897 quick-pwm slave controllers for multiphase, step-down supplies ______________________________________________________________________________________ 31 32l qfn .eps package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)
max1887/max1897 quick-pwm slave controllers for multiphase, step-down supplies 32 ______________________________________________________________________________________ package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)
max1887/max1897 quick-pwm slave controllers for multiphase, step-down supplies maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 33 ? 2002 maxim integrated products printed usa is a registered trademark of maxim integrated products. qfn thin 5x5x0.8 .eps d2 (nd-1) x e e d c pin # 1 i.d. (ne-1) x e e/2 e 0.08 c 0.10 c a a1 a3 detail a 0.15 c b 0.15 c a document control no. 21-0140 package outline 16, 20, 28, 32l, qfn thin, 5x5x0.8 mm proprietary information approval title: c rev. 2 1 e2/2 e2 0.10 m c a b pin # 1 i.d. b 0.35x45 l d/2 d2/2 l c l c e e l c c l k k l l 2 2 21-0140 rev. document control no. approval proprietary information title: common dimensions exposed pad variations 1. dimensioning & tolerancing conform to asme y14.5m-1994. 2. all dimensions are in millimeters. angles are in degrees. 3. n is the total number of terminals. 4. the terminal #1 identifier and terminal numbering convention shall conform to jesd 95-1 spp-012. details of terminal #1 identifier are optional, but must be located within the zone indicated. the terminal #1 identifier may be either a mold or marked feature. 5. dimension b applies to metallized terminal and is measured between 0.25 mm and 0.30 mm from terminal tip. 6. nd and ne refer to the number of terminals on each d and e side respectively. 7. depopulation is possible in a symmetrical fashion. 8. coplanarity applies to the exposed heat sink slug as well as the terminals. 9. drawing conforms to jedec mo220. notes: 10. warpage shall not exceed 0.10 mm. c package outline 16, 20, 28, 32l, qfn thin, 5x5x0.8 mm package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)

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